In article <3E8813F1.502D4ED8 / jandecaluwe.com>,
Jan Decaluwe  <jan / jandecaluwe.com> wrote:
>Craig Selton wrote:
>> 
>> This looks interesting.  You've managed to make a standard scripting
>> language look convincingly like an HDL.  I've seen some other similar
>> efforts recently (like one that uses Python) but, while interesting,
>> they don't end up looking like an HDL - in most cases they end up
>> forcing the HDL designer to learn a totally different style.
>
>At least for MyHDL (my Python HDL attempt that you refer to), this
>should
>not be the case. Just substitute "while 1" for "process" or "always",
>and "yield" for "wait", and you're done :-) Also, see the section
>on RTL modeling in the MyHDL manual.

That's kind'a how I saw it too...

>
>Moreover, I believe emphasis on superficial syntax similarities can
>make things confusing, as the semantics may still be different.
>For example, the very first "process" example in the RHDL manual has
>a global sensitivity list *and* an internal wait statement, something
>which is forbidden in VHDL. It's forbidden for good reasons I believe,
>because if I try to imagine how this is supposed to work, I get
>thoroughly confused .. 

Hmmm... maybe I should change this as it's not a very realistic example ( 
I essentially added a 'wait' to an already existing example ).  The first 
time the counter signal changes, the process is initiated and then it 
waits for three clk_events before proceeding with the rest of the 
code in the process.  Of course, the problem is that the next time 
the counter changes and initiates that process it will only run 
till the wait and then suspend since clk_events will never be equal 
to 3 again.  Makes sense to me (and probably only to me ;-) but perhaps I 
should disallow this.

Phil