RHDL 0.4.2 is now available at:
http://www.aracnet.com/~ptkwt/ruby_stuff/RHDL/index.html

What is it:

An HDL (Hardware Description Language) built on the Ruby scripting 
language (I prefer to call Ruby an agile language).  It tends to look a 
lot like VHDL.  Here's an example of a simple state machine:

require 'RHDL'
class WashMachine < RHDL::Design
  include RHDL
  def initialize(clk,rst)
    super()
    state_sig = Signal(StateType(:start,:wash,:rinse,:spin,:stop))
    define_behavior {
       process(clk,rst) {
         #async reset:
         if rst == '1'
           puts "RESET"
           state_sig << :start
         elsif clk.event && clk == '1'
           case state_sig.inspect
           when :start
             state_sig << :wash
           when :wash
             state_sig << :rinse
           when :rinse
             state_sig << :spin
           when :spin
             state_sig << :stop
           when :stop
             #stay here till reset
           else
             raise "invalid state! #{state_sig.state}"
           end
         end
       }
       process(state_sig) {
         #prints message whenever state_sig changes:
         puts "Current state is: #{state_sig}"
       }
    }
  end
end

#instantiating and simulating:

  include RHDL
  include TestBench

  #create a clock that starts out low and toggles every 2 time periods:
  clk = ClkGen.generator('0',2,2)
  rst = Signal(Bit.new('1')) #initially reset
  fsm = WashMachine.new(clk,rst)

  puts "step: 0"
  step
  puts "step: 1"
  step
  puts "step: 2"
  step
  rst << '0' #turn off reset
  18.times do |i| 
    puts "step: #{i+2}"
    step
  end

....like I said, it looks a lot like VHDL.  (an idea for future development 
would be to add a Verilog module so that you could code in a VHDL or 
Verilog style).


What's it good for: 

* Teaching HDL concepts including internal simulation concepts (the 
  full source code is available and it is relatively small)
* As a high-level verification language (HVL) (with a few more 
  additions)


What's changed since the last release:

* The website has been _much_ improved (there really wasn't a website 
  before, just a download link :)
* No new's is good new's:  Used to be you had to do things like:
    sig = Signal.new(Bit.new('0'))
  Now, I've added some helper methods so that you can do:
    sig = Signal(Bit('0'))
  ... which saves a good bit of typing.
* The Bit and BitVector classes have pretty much been rewritten and 
  (hopefully) much improved.  I've changed the operators so that they 
  return new objects.  I've also endeavored to make the operators more 
  polymorphic so that you can add an Integer to a BitVector, for example.
* created a user's guide and much improved the website.
* added a ClkGen class to make it easier to create clock signals
* added a StateType class which is kind of like an enumerated state type.

I'm very interested in getting feedback on this, so if you give it a try 
please drop me an email.

Phil