Ruby-VPI is a Ruby interface to Verilog VPI. It lets you create
complex Verilog test benches easily and wholly in Ruby.

  Website:   http://ruby-vpi.rubyforge.org

  Install:   gem install ruby-vpi


Version 12.0.0 (2006-12-07)

Summary

This release adds support for the test/spec library, fixes
some bugs, and improves the user manual and generated
tests.

Notice

   Icarus Verilog 0.8 has been demoted to a mostly
    acceptable status.

   Generated Verilog benches no longer supply the -w
    option to the $ruby_init task.

   The ruby-vpi/runner_proxy library now invokes test
    runners
       just before exiting. Thus, you can invoke tasks in
        the main Rakefile before the test runners are
        invoked.
       located within any directory that is a descendant
        of the current working directory.

   The SIMULATOR_ARGS parameter of generated runners has
    been renamed to SIMULATOR_ARGUMENTS for clarity.

   The automated test generator
       no longer displays the backup status indicator.
       now supplies a third argument to the MERGER
        command.
       no longer replaces existing files with newly
        generated content during the update action.
        Instead, it now writes the newly generated output
        to a .new file and then invokes the MERGER command.

Detail

   The Vpi::Handle class has two new methods: x! and z!,
    which set the handles logic value to unknown and high
    impedance respectively.

   The tests for the simple up-counter example were
    randomly failing because the specifications were not
    asserting the designs reset signal long enough. So the
    design was getting into weird states and behaving in a
    non-deterministic way. This problem has been fixed.

   The user manual has been revised and some minor issues
    have been fixed.

Test generation

   The automated test generator accepts new command-line
    options:
       test-unit
       test-spec
       tspec

   The automated test generator was crashing when parsing
    module parameters of an input file which did not have
    any module parameters. This has been fixed.

   Generated Verilog benches now contain simpler clock
    generation code.

   Generated runners now contain
       a :setup task which is invoked before the simulator
        runs. It can be used to make preprations, such as
        converting Verilog header files into Ruby, for the
        simulation.
       better explanations to accomodate new users.

   Specifications generated in the generic format no
    longer contain a class that is instantiated in the
    generated Ruby bench.

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