In article <440013A1.5030005 / capitain.de>,
Pit Capitain  <pit / capitain.de> wrote:
>Phil Tomson schrieb:
>> 
>> Here's what I finally came up with:
>> 
>>   class AndGate < RHDL
>>     inputs :a, :b
>>     outputs :out
>>     init {
>>       somevar = 0
>>       define_behavior {
>>         out << (a & b)
>>         puts "somevar is: #{somevar}"
>>         somevar +=1
>>       }
>>     }
>>   end
>
>This is a nice looking compromise.
>
>> BTW: I'm thinking of using '<=' for assignment instead of '<<' since '<=' has 
>> lower precedence than '<<' and that would allow:
>>   out <= a & b  #parens not required
>
>I think you know this already, but if you would use the same assignment 
>operator for variables, you could omit the init method.
>

Right.  I've considered that option, but for now I think it's better to make 
the distinction between variables and signals (other HDLs make the distinction 
as well where variables are considered to change 'immediately' while signals 
change at the end of the block evaluation).

The other change I'm considering is hiding the explicit class 
definition, like so:

  AndGate = Circuit {
    inputs :a, :b
    outputs :out
    init {
      somevar = 0
      define_behavior {
        out <= a & b
        puts "somevar is: #{somevar}"
        somevar +=1
      }
    }
  }
  g=AndGate.new(a,b,a_and_b)

Where Circuit is defined something like:

  def Circuit &b
    #...
    klass=Class.new(RHDL) &b
    #...
    klass
  end

That would hide a little more 'Rubyness' behind the DSL curtain.

Phil