In article <84fb38e305080207325f7a0fb / mail.gmail.com>,
tsuraan  <tsuraan / gmail.com> wrote:
>On 01/08/05, Eric Mahurin <eric_mahurin / yahoo.com> wrote:
>> I'd be interested.  I'm in the IC design industry.  I wrote a
>> verilog-2005 parser using antlr/java about a year ago (never
>> released it).
>
>I'm wondering, what did you use this for?  I've been looking for free
>(open source preferably) synthesis tools for my FPGA collection, and
>have found nothing.  I figured it was because "compiling" verilog to
>netlists for use on an FPGA is really hard, and the FPGAs themselves
>are not well documented internally.  

Certainly and this is by design.  Xilinx and Altera are very secretive, 
they don't want people reverse engineering their FPGAs.  Not that it would 
be a huge problem because they're well protected by patents.  

That said, I believe you can use Icarus (open source Verilog 
simulator and now synthesis tool) to synthesize to some of the older 
Xilinx architectures.  Also, it can't be impossible to get the needed 
information (Synplicity, for example, makes FPGA synthesis tools that 
target Xilinx, Altera and others' parts), but there may be NDA forms to 
sign.  I suspect the bitstream files are the tricky part.

> What do you do with a Verilog or
>VHDL parser, if you can't actually implement your designs?
>

Actually there are lots of possibilities if you have Verilog/VHDL parsers:

1) You could create translators between the two or to cycle-based 
C or SystemC.
2) You could create a testbench generation tool.  The tool would look at 
your toplevel entity/module and then it could create the skeleton for your 
testbench.  Of course, you don't need a full parser for this, but if you 
have one it'll make things easier.
3) It would be possible to create verification and code analysis tools.
4) Synthesis/Tech mapping.  Nothing would stop you from creating 
VHDL/Verilog or EDIF netlists (gate level).  Because Ruby is a very 
flexible language it would be interesting to use it to develop an 
experimental synthesis platform where you could easily try new algorithms, 
datastructures, etc.

....lots of possibilities.


Phil