On 01/08/05, Eric Mahurin <eric_mahurin / yahoo.com> wrote:
> I'd be interested.  I'm in the IC design industry.  I wrote a
> verilog-2005 parser using antlr/java about a year ago (never
> released it).

I'm wondering, what did you use this for?  I've been looking for free
(open source preferably) synthesis tools for my FPGA collection, and
have found nothing.  I figured it was because "compiling" verilog to
netlists for use on an FPGA is really hard, and the FPGAs themselves
are not well documented internally.  What do you do with a Verilog or
VHDL parser, if you can't actually implement your designs?